1. Field of the Invention
The present invention generally relates to a method for forming a crack stop structure in a scribe line. In particular, the present invention is directed to a crack stop structure filled with s single dielectric material and a method for forming the crack stop structure in a scribe line.
2. Description of the Prior Art
Semiconductor manufacturers have been trying to shrink the size of transistors in integrated circuits (IC) in order to improve chip performance. This has resulted in an increased speed and device density. For sub-micron technology, the RC delay becomes the dominant factor. To facilitate further improvements, semiconductor IC manufacturers have been forced to turn to new materials for reducing the RC delay by either lowering the interconnect wire resistance, or by reducing the capacitance of the inter-layer dielectric (ILD) material. A significant improvement was achieved by replacing aluminum (Al) interconnects with copper, which has −30% lower resistivity than that of Al. Further advances may be accomplished by the substitution of other low-k dielectric materials.
In prior art aluminum interconnect technology, where Al forms a self-passivating oxide layer, a crack stop is formed to prevent cracks from traversing the BEOL dielectrics into the IC chip. However, one disadvantage associated with the use of low-k dielectrics is that almost all low-k dielectric materials possess a relatively lower mechanical strength than that of conventional silicon oxide dielectrics such as FSG or USG.
The use of low-k dielectrics poses another problem for the industry in that the adhesion ability, either at the interface between two adjacent low-k dielectric layers or at the interface between a low-k dielectric layer and a dissimilar dielectric layer, is inadequate to meet the requirements of subsequent wafer treatment processes such as wafer dicing, which is typically performed to mechanically cut a semiconductor wafer into a number of individual IC chips.
The technology of dicing has been developed to a high standard. One restriction of dicing is that cracks extend laterally from the dicing line into the semiconductor and insulating materials. Due to these cracks, moisture and contamination are free to penetrate active circuitry and start degrading the electrical device performance by a drastic amount. Even today, the generation of cracks is the most significant limitation with respect to the minimization of circuit chips. In addition, these cracks also represent significant reliability risks, since they tend to grow and widen under thermal and mechanical stress and thus eventually imperil the functionality of the integrated circuit.
It has been found that the so-called “interface de-lamination” phenomenon occurs between low-k dielectric layers during or after the wafer dicing process is performed, which causes performance degradation of the IC chips. In light of the above, the industry still requires a solution to the undesired propagation of interface de-lamination between low-k dielectric layers originating from the wafer dicing process.